1. Field
Embodiments of the present invention generally relate to techniques for designing and manufacturing integrated circuits (ICs). More specifically, embodiments of the present invention relate to a technique for adjusting assist feature placements in an IC layout to correct assist-feature-printing errors.
2. Related Art
The dramatic improvements in semiconductor integration densities in recent years have largely been made possible by corresponding improvements in semiconductor manufacturing technologies.
One such manufacturing technology involves placing assist features in an IC mask layout (a “layout” hereinafter) to improve consistency of manufacturing results if one or more physical processes change during IC manufacturing. Note that the amount of drift of a process parameter which does not cause the manufacturing results to go out of the design specifications is often referred to as a “process window”. For example, during an optical lithography process, the range of focus drift around an in-focus condition can be the process window. Assist features are added to the layout to improve the process window.
Assist features are not supposed to appear in the printed image on the wafer. However, sometimes assist features are actually printed on the wafer, which leads to “assist-feature (AF)-printing errors.” Such AF-printing errors are undesirable and therefore need to be avoided. Typically, wider assist features have better performance on the process window. However, such wider assist features are also more likely to be printed. Consequently, placing assist features in a layout requires a balance between placing assist features in a way to improve the process window and at the same time preventing these assist features from printing in the final mask images.
Hence, what is needed is a method and apparatus for effectively eliminating AF-printing errors while achieving satisfactory through-process behavior of printed patterns without the above-described problems.